Forming semiconductor devices, e.g., power semiconductor devices including power semiconductor diodes, IGFETs (insulated gate field effect transistors) and IGBTs (insulated gate bipolar transistors) includes formation of semiconducting elements in a semiconductor wafer and then separating single semiconductor dies of semiconductor devices from the wafer by a separation process, e.g., dicing, etching, sawing or breaking. The separation process may adversely affect a semiconductor crystal lattice along lateral surfaces of the semiconductor dies exposed by the separation process. Edge structures such as chipping stoppers, glass frames and passivation layers typically protect the semiconductor dies against chipping, against crystal damage spreading from the lateral surface, e.g., cleavage planes expanding in high temperature treatments, and against impurities entering the semiconductor body through the lateral surfaces. In addition or alternatively, termination structures including conductive, dielectric and/or semiconducting regions in a termination region of the semiconductor die aim at keeping the lateral surface free from electric fields such that lattice defects and impurities existent along the lateral surface have no or only low impact on the device characteristics.
It is desirable to reduce the impact of dicing and edge effects on the electric characteristics of semiconductor devices at low effort.